STUDY OF THE SUITABLE VALUE OF DEAD-TIME BETWEEN CONTROL SIGNALS OF TRANSISTORS FOR A SERIES-RESONANT INVERTER WITH PHASE-SHIFT CONTROL IN INDUCTION HEATING SYSTEMS

Induction heating provides contactless, energy-efficient, accurate, and fast heating of electrically conductive materials. Due to its advantages, IH is increasingly used in different fields such as industry, medicine, and the household sector. High-frequency transistor converters for the induction heating system are often based on series-resonant inverters. This paper analyzes a phase-shift-controlled voltage-source series-resonant inverter for induction heating systems. Mathematical analysis was performed in order to obtain the expressions that describe the output current of the phase-shift-controlled series-resonant inverter in the steady-state mode. Based on the analysis and the obtained expressions of the output current, analytical expressions of the dead-time between the transistors’ control signals of the SRI are obtained. The analytical expressions for determining the value of the dead-time are obtained for two cases: 1) zero value of the phase-shift; 2) the phase shift is greater than zero. To verify the obtained analytical expressions of the output current, validation was performed in the MATLAB/Simulink environment by comparing the peak current values. The verification showed the high accuracy of the obtained expressions, the deviation between the calculated and simulated values of the peak current is less than 0.1 %. The made simplifications of the dead-time expressions also were verified by calculation, the deviation between the calculated values of the drain-to-source voltage at the end of the commutation and the expected value is no more than 3.6 %. The SRI prototype has been designed and implemented in order to validate the analytical and simulation results.


Introduction
The use of voltage-source series-resonant inverters (SRIs) as power supplies for induction heating systems is a very cost-effective solution since regulation of the output current or power of the SRI is possible by the SRI itself with using various control methods. Many different control techniques have been proposed for regulating the SRI output current such as pulse-width modulation [1,2], pulse-frequency modulation [3,4], phase-shift control [5][6][7][8][9], pulse-density modulation (PDM) [10][11][12], etc. To achieve high efficiency of the SRI and control over a wide power range, it is sensible to use control methods that can provide zero-voltage switching (ZVS) and/or zero-current switching (ZCS).
Recently, the PDM control method is widely applied, usually when the SRI load quality factor is high. However, this method has its disadvantages. The main one is amplitude fluctuations of the SRI output current, which is a serious problem at low values of the quality factor. The second one -the current control is limited by the available combinations of the PDM parameters, when the required pulse density value cannot be realized with one of these combinations, the control system will change two nearby PDM combinations. Thus, the power regulation is not smooth. To reduce these disadvantages, enhanced PDM methods have been proposed [13][14][15]. But the reduction in fluctuation achieved is not significant or there is a dc component at the SRI output voltage. Another approach to reducing fluctuations is using a converter with a modular topology [16,17] or an extended topology [18]. But in both cases, more transistors are required.
The phase-shifted (PS) control method is a well-known and suitable method for the SRI, which can be used for both low and high values of the quality factor. Thus, in order to mitigate Engineering the disadvantages of the PDM control method, some authors combine the PDM and PS controls. In [19,20] authors combine the PDM and PS controls to provide more smooth power regulation. In [21], a combined control method based on the phase-shift and PDM controls is proposed to reduce current fluctuations.
To ensure the ZVS and ZCS operation of the SRI transistors, it is necessary to provide a certain value of the dead-time between the control signals of the SRI transistors. It should be noted that most authors carry out a mathematical analysis of the SRI output current, taking into account only the first harmonic of the square-wave output voltage of the SRI, and the obtained expressions are used to determine the minimum value of the dead-time [10,13,15,[22][23][24][25]. However, with a low value of the quality factor, using this approach can lead to a significant error in determining the value of the dead-time. Thus, the task is to determine the equation of the minimal dead-time value for the SRIs with PS control, correct for different values of the quality factor. This paper presents a mathematical analysis of a phase-shift-controlled series-resonant inverter (PSC-SRI) for induction heating systems. To ensure the ZVS and quasi-ZCS operation of the PSC-SRI transistors, expressions of the dead-time between control signals of the PSC-SRI transistors were obtained analytically. The reliability of the analysis and the accuracy of the obtained expressions were verified by comparing the simulation results with the calculations. Fig. 1 shows a typical configuration of a voltage-source inverter and Fig. 2 depicts waveforms of the output current i O and the output voltage υ O of the PSC-SRI, as well as the control signals of the SRI transistors (Q 1 -Q 4 ). The SRI topology is a full-bridge with four MOSFETs Q 1 -Q 4 . A high-frequency DC capacitor C c is used to reduce the spike voltage across the SRI transistors.  The SRI operates slightly above the resonant frequency. Thus, the output current i O of the SRI legs the output square-wave voltage υ O of the SRI. Body diodes D 1 -D 4 , respectively, of the transistors Q 1 -Q 4 conduct current after then the parasitic capacitance of the transistors is discharged. During the conductivity interval of a diode, the transistor turns-on at zero voltage. Engineering Thus, there are no problems with the transistors overlap diode reverse recovery problem. The phase portion β, where the voltage υ O and current i O are in the opposite direction, is essential to determine the ZVS operation. The dead-time T DT between the control signals of the transistors must be set sufficient to avoid overlap of the transistors. Typically, the minimum value of T DT depends on the maximum value of β. Fig. 3 shows an equivalent SRI circuit with secondary components reflected to the primary side, and Fig. 4 depicts the waveforms of i O and υ O under the assumption that the MOSFET's output capacitance is small compared to the resonant capacitor, as well as the duration of the phase portion β; thus, its effect on the output current and voltage when switching the transistor is small and is negated.   (Fig. 4); the SRI output current i O (t) and the resonant capacitor voltage υ C (t) in the time domain are defined as:

Materials and methods 1. Analytical modeling of the PSC-SRI
where ω d is the damped frequency, and sgn(V d ) is the sign function of V d are given by: Taking into account that I 0a = I 0c = 0 and that i O at stages (a) and (b) is equal to (c) and (d), but with sing minus, (1) and (2) can be represented as follows: .. ; In the steady-state mode, values of i O and υ C at the end of one time-interval must be equal to the values of i O and υ C at the beginning of the next time interval. Since the initial values of i O and υ C at the beginning of the intervals T A -T C are given by: where Equations (5), (7)-(10) allow to analytically simulate the SRI output current for various values of ϕ. Fig. 5 shows the detailed waveforms of the inverter output current i O and the transistor drain-to-source voltage υ Q taking into account the output capacitance of each MOSFET. As can be seen from Fig. 5, β time for the current with a higher peak value can be reduced. However, the value of T DT has to be set sufficiently to ensure ZVS with the minimum peak value of i O .

Discussion on dead-time
If no additional drain-to-source capacitors are added to the MOSFETs, the drain-to-source voltage υ DS during the commutation within the phase portion β is given by: where C oss is the MOSFET's output capacitance, T β is the time at which the MOSFET starts to turn off. In the case of SRI operating without shifting between the transistors control signals (ϕ = 0), the output current is given by the following equation: where I m is the current amplitude value is given by: Therefore, the drain-to-source voltage υ DS4 during the commutation is given by: The drain-to-source voltage has to reach V d up to t = 0 at some set point t = T 1 (T 1 is the time at which υ DS has to reach the dc-link voltage V d at the minimum peak value of i O ). The duration of the interval ΔT 1 (the interval between the moments when the drain-to-source voltage reaches V d and the current crosses zero) has to be selected sufficiently to turn on the MOSFET within this interval. Since in the vicinity of the point t = T O /2, the value of ω d cos(ω d t) is a lot more than the value of (R/2L) sin(ω d t) and the values of e An analytical expression for the minimum value of T DT , required to achieve ZVS, is given by: Thus, (16) makes it possible to determine the minimum value of T DT in the case when ϕ = 0, and it does not depend on the value of the current i O .

Case when ϕ>0
In the case when ϕ > 0, the transistor commutation occurs at a current i O within stages (b) and (d ). To obtain the voltage and currents waveforms, which are shown in Fig. 1, the SRI must operate at a frequency that is higher than the damped frequency.

Engineering
In the continuous-time domain, the output current can be represented as follow: where A m is the current amplitude value is given by: Therefore, the drain-to-source voltage υ DS during the commutation is given by: Since it is possible to simplify (19): 2 2 sin . (20) In this case, the mathematical expression for the minimum value of T DT , required to achieve ZVS, is given by: Expression (21) is more complicated than (16), and its value depends on the value of the current amplitude, which is determined by (18).

Results and discussion 1. Simulation and calculation results
To investigate the validity of the equations obtained by the mathematical analysis in this paper, the applied output voltage of the PSC-SRI to the series-resonant circuit is simulated in MATLAB/Simulink environment. Fig. 6 shows simulation circuit models for the case when ϕ = 0 and the case when ϕ > 0, in Fig. 6, a and b, respectively. In Table 1 are presented parameters used for simulation as well as the results of the simulation, calculation, and verification. The accuracy of the obtained analytical expressions of the output current was verified by comparing the calculated peak output current value using (12) and (17) where Cal.I p is the calculated peak current value determined from (12) and (17) as a local extremum and Sim.I p is the peak current value obtained as a result of the simulation. Engineering Fig. 6. Simulation circuit models: a -case when ϕ = 0; b -case when ϕ>0 Table 1 Parameters used for simulation and calculation as well as results of simulation, calculation, and verification As can be seen from Table 1, the deviation δ between the calculated and simulated values of the peak current is less than 0.1 %, which indicates the reliability of the presented analytical expressions of the output current. The deviation δ can be explained by the accuracy of setting the value of the required operating frequency f O = 1/T O , which was used in the calculations and modeling. Engineering Table 2 shows the values of T DT calculated by (16) and (21) for various values of ϕ and Q. The values of ΔT 1 and C oss were taken 500 ns and 1000 nF, respectively. Also, the same parameters were used to calculate the values of T DT , which are shown in Table 1. Furthermore, Table 2 shows the calculated value of υ DS at t = T 1 by (14) and (19), as well as the deviation Δ between the calculated value of υ DS at t = T 1 and the expected value V d = 1.
The value of Δ is given by: To calculate υ DS (T 1 ), the values of T 1 and T β are determined as follows: The calculated value of Δ is not more than 3.6 %. Thus, it can be argued that simplifications of (14) and (19) don't lead to a significant error in determining the value of T DT . And the calculated values of T DT are not less but somewhat more than necessary, therefore, there is no transistors' overlapping during the commutation.

2. Experimental results and discussion
To verify the results of simulation and calculation a prototype setup has been developed. Fig. 7, 8 show the experimental waveforms obtained by this setup. In the following experiments, the values of ΔT 1 and T DT were set to 500 ns 510 ns, respectively. The phase-shift ϕ was varied from 0 up 135 degrees, thus the operating frequency during the experiments ranged from 30.8 kHz to 33 kHz. The calculated value of Q was close to 6.3. Fig. 8 shows the experimental waveforms of the drain-to-source voltage and the SRI output current during commutations. For the regulation range of ϕ from 0 up to 135 degrees, the ZVS commutation of the SRI transistor can be confirmed. In the following experiments, the observed duration of the drain-to-source voltage from Fig. 8, a- he above leads to the conclusion that the value of T DT was calculated with sufficient accuracy, which particularly depends on the taken value of C oss for calculation. А limitation of this study is that the resulting expressions are suitable for the SRI with the PS control method, but not for the SRI with the combined PS-PDM control method (because a free-wheeling interval, which is due to using the PDM control method, affects the SRI output current). Thus, the directions for future research that needs to be carried out are: 1) development of the PS-PDM with the controlled dead-time value; 2) determine the influence of the current fluctuations when using the combined PS-PDM control method on the required minimal value of the dead-time.

Conclusions
This paper analyzes a phase-shift-controlled voltage-source series-resonant inverter for induction heating systems. A detailed mathematical analysis was presented, obtaining the expressions for the inverter output current in the steady-state mode. Based on the analysis and Engineering the obtained expressions of the output current, analytical expressions of the dead-time between the transistors' control signals of the SRI are obtained. To verify the obtained analytical expressions of the output current, validation was performed in the MATLAB/Simulink environment by comparing the peak current values. The verification showed the high accuracy of the obtained expressions, the deviation between the calculated and simulated values of the peak current is less than 0.1 %. The made simplifications of the dead-time expressions also were verified by calculation, the deviation between the calculated values of the drain-to-source voltage at the end of the commutation and the expected value is no more than 3.6 %. Future work on this topic may include a controlled dead-time for PSC-SRI as well as determine the influence of current fluctuations in the case of using the combined PS-PDM control method on the required minimal value of the dead-time.