Keywords: FPGA, Advanced Encryption Standard, VHDL, security by AES, 256-AES, encryption by AES


The increase number of eavesdropping or cracker to attack the information and hack the privacy of people. So, the essential issue is making system capable of ciphering information with rapid speed. Due to the advance in computer eavesdropping and cracker that made them to analysis the way of ciphering in rapid speed way. The development in the computer especially in the rapid processer in the last decade create the breaching of any system is a matter of time. Owing to most of breaching ways are based on analysis of system that requireы to be breached and to try brute force on that system to crack it. However, the lacking of influential processers that are capable of breaching system since earlier processors are limit to number of instructions. It can be done in second, which was not sufficient trying to break the system using brute force. In addition, the time required is far away from getting valuable messages in the time that needed. So, the research gives the focus on performing rapid system for ciphering the information rapidly and changing the ciphering every few milliseconds. The changing of ciphering in every millisecond helps system form preventing the eavesdropping and cracker from imposing brute force on the system and hacking the messages and images. The system that created is based on Advanced Encryption Standard (AES), which is it very best performing algorithm in ciphering and deciphering since it doesn’t need complex mathematical formula. The research is about designing system that capable of performing AES by using high processer designed on Field programmable gate Area (FPGA). The ciphering of AES using FPGA helps minimize the time required to cipher the information. Also, the research will focus on ciphering and deciphering of images by AES using FPGA


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Author Biographies

Hind Ali Abdul Hasan, Alkut College University

Department of Laser & Optoelectronics Engineering

Safaa Maijd Mohammed, Al-Farahidi University

Department of Medical Instrumentation

Noor Hayder Abdul Ameer, University of Technology

Department of Computer


Ekert, A. K., Huttner, B., Palma, G. M., Peres, A. (1994). Eavesdropping on quantum-cryptographical systems. Physical Review A, 50 (2), 1047–1056. doi:

Omran, S. S., Al-Hillali, A. A. (2015). Quarter of Iris Region Recognition Using the RED Algorithm. 2015 17th UKSim-AMSS International Conference on Modelling and Simulation (UKSim). doi:

Babitha M.P., Babu, K. R. R. (2016). Secure cloud storage using AES encryption. 2016 International Conference on Automatic Control and Dynamic Optimization Techniques (ICACDOT). doi:

Barriga, L., Blom, R., Gehrmann, C.,Naslund, M. (2000). Communications security in an all-IP world. Ericsson review, 2, 96–107.

Nishikawa, N., Amano, H., Iwai, K. (2017). Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU. Lecture Notes in Computer Science, 273–287. doi:

Abdullah, A. M. (2017). Advanced encryption standard (AES) algorithm to encrypt and decrypt data. Cryptography and Network Security.

Maharjan, R., Shrestha, A. K., Basnet, R. (2019). Image Steganography: Protection of Digital Properties against Available at:

Peake, T. M. (2005). Eavesdropping in communication networks. Animal Communication Networks, 13–37. doi:

Alanazi, H.O., Zaidan, B.B., Zaidan, A.A., Jalab, H. A., Shabbir, M.,Al-Nabhani, Y. (2010). New Comparative Study Between DES, 3DES and AESwithin Nine Factors. Journal of Computing, 2(3), 152–157.

Stallings, W. (2011). Cryptography and Network Security Principles and Practice.Prentice Hall.

Ueno, R., Morioka, S., Homma, N., Aoki, T. (2016). A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths. Cryptographic Hardware and Embedded Systems – CHES 2016, 538–558. doi:

Banik, S., Bogdanov, A., Regazzoni, F. (2017). Compact circuits for combined AES encryption/decryption. Journal of Cryptographic Engineering, 9 (1), 69–83. doi:

Jumma, L. F.,Omran, S. S. (2018). Design Of Superscalar SHA-1 & SHA-2 MIPS Processor Using FPGA. Association of Arab Universities Journal of Engineering Sciences, 25(3), 88–99.

Omran, S. S., Al-Hilali, A. A. (2018). Comparative Study Between Different Rectangle Iris Templates. 2018 International Conference on Advanced Science and Engineering (ICOASE). doi:

Al-Hilali, A. A., Jumma, L. F., Amory, I. A. (2019). High-Quality Image Security Implementation Using 128-Bit Based on Advanced Encryption Standard algorithm. Journal of Southwest Jiaotong University, 54 (6). doi:

Çavuşoğlu, Ü., Kaçar, S., Zengin, A., Pehlivan, I. (2018). A novel hybrid encryption algorithm based on chaos and S-AES algorithm. Nonlinear Dynamics, 92 (4), 1745–1759. doi:

Messerges, T. S. (2001). Securing the AES Finalists Against Power Analysis Attacks. Fast Software Encryption, 150–164. doi:

Elsherif, S., Mostafa, G., Farrag, S., Alexan, W. (2019). Secure Message Embedding in 3D Images. 2019 International Conference on Innovative Trends in Computer Engineering (ITCE). doi:

Al-Fedaghi, S., Alsulaimi, M. (2018). Privacy Thinging Applied to the Processing Cycle of Bank Cheques. 2018 3rd International Conference on System Reliability and Safety (ICSRS). doi:

Zodpe, H., Sapkal, A. (2020). An efficient AES implementation using FPGA with enhanced security features. Journal of King Saud University - Engineering Sciences, 32 (2), 115–122. doi:

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How to Cite
Hasan, H. A. A., Mohammed, S. M., & Ameer, N. H. A. (2021). ADVANCED ENCRYPTION STANDARD USING FPGA OVERNETWORK. EUREKA: Physics and Engineering, (1), 32-39.
Computer Science